1. Field of the Invention
The present invention relates to a semiconductor memory device such as a nonvolatile memory represented by a flash EEPROM in which its memory cell is constituted of a nonvolatile memory cell transistor and a select transistor and a nonvolatile memory embedded logic integrated circuit, and a method of manufacturing the semiconductor memory device.
2. Description of the Related Art
There has been known a nonvolatile memory which is constituted of the nonvolatile memory cell transistor having a stacked gate structure containing a charge storage layer and a control gate layer and the select transistor for selecting a specific memory cell transistor at the time of program, read or erase for the memory cell transistor. In this nonvolatile memory, a drain diffusion layer of a memory cell transistor is connected to a bit line and a source diffusion layer of a select transistor is connected to a source line so as to share the source diffusion layer of the memory cell transistor and the drain diffusion layer of the select transistor. That is, each memory cell has a structure in which the memory cell transistor and the select transistor are connected in series between the bit line and the source line.
The source diffusion layer and drain diffusion layer of the memory cell transistor and the select transistor are formed by introducing impurity into a device region on a semiconductor substrate. To ensure a sufficiently large memory cell current, resistance values of the source and drain diffusion layers need to be reduced by increasing the impurity concentration of the source and drain diffusion layers. However, if the impurity concentrations of the source and drain diffusion layers shared by the memory cell transistor and the select transistor are increased, a leakage current larger than a capacity of supply from a charge pump circuit is generated by a gate induced drain leakage (GIDL), so that no desired potential can be supplied to the nonvolatile memory.
In the meantime, Jpn. Pat. Appln. KOKAI Publication No. 2006-309890 has disclosed a nonvolatile semiconductor memory device in which the select transistor is connected in series to the memory cell transistor while the select transistor has a two-layer gate structure and, by driving the voltages of each gates of the select transistor individually, the absolute value of a generated voltage level of the gate voltage generating portion for the select transistor is decreased to reduce consumption current.
Further, Jpn. Pat. Appln. KOKAI Publication No. 11-214547 has disclosed a nonvolatile semiconductor memory device in which the source diffusion layer is constituted of a high concentration source diffusion layer and a first low concentration source diffusion layer which is located adjacent to the side portion on the floating gate side of the high concentration source diffusion layer and has a lower impurity concentration than the high concentration source diffusion layer, and the first low concentration source diffusion layer has a shallower coupling than the high concentration source diffusion layer so as to suppress an increase in leakage current.
Jpn. Pat. Appln. KOKAI Publication No. 2000-114404 has disclosed a flash memory in which, of a channel region under the floating gate, a channel region adjacent to the impurity diffusion layer on the drain side has a p+ region where the concentration of p-type impurity is the highest in the channel region and a p+ region provided at a portion not covered by the floating gate in the channel region.
Further, Jpn. Pat. Appln. KOKAI Publication No. 2002-231832 has disclosed a nonvolatile semiconductor memory device which includes a memory cell unit containing a memory cell transistor having a stacked gate structure composed of a floating gate and a control gate, and a select gate transistor in which one of the source/drain diffusion layers is connected to a bit line or a source line while the other is connected to the memory cell unit, wherein the shape of the source/drain diffusion layers of the select gate transistor is asymmetrical under a gate electrode of the selective gate transistor.